FPGA technical reference designs (TRDs)

Topic provides FPGA technical reference designs (TRD) for its boards. These reference designs can be found here

Note

When building the XDPZU design, additional licenses are required to build the design.

Generate and build Vivado project

The TRDs are provided as a .zip file. To build the TRD first unzip it. The .zip file contains a shell file (.sh) and a batch file (.bat) so it can be run on either a Linux or a Windows machine. The instructions on how to build for both OSses are below.

Instructions for Ubuntu

  1. Open a terminal window

  2. Step into the unzipped TRD directory

    cd ${TRD_DIR}
    
  3. Source Vivado’s settings script so that Vivado can be run from the terminal (path to installation directory might vary)

    source /opt/Xilinx/Vivado/2021.1/settings64.sh
    
  4. Set the FPGA_FAMILY environment variable to match the right FPGA (ex: xczu9eg).

    Tip: Run the next step (generate_bitstream.sh) without setting the FPGA_FAMILY variable to see the value options.

    export FPGA_FAMILY=xczu9eg
    
  5. Run the shell script to generate and build the TRD

    ./generate_bitstream.sh
    

    This will generate a directory with the FPGA name and the TRD will be created in that directory.

Instructions for Windows 10

  1. Open a command prompt

  2. Step into the unzipped TRD directory

    cd %TRD_DIR%
    
  3. Execute Vivado’s settings64.bat so that Vivado can be run from the command prompt (path to installation directory might vary).

    C:\Xilinx\Vivado\2021.1\.settings64-Vivado.bat
    
  4. Set the FPGA_FAMILY environment variable to match the right FPGA family (ex: xczu9eg).

    Tip: Run the next step (generate_bitstream.bat) without setting the FPGA_FAMILY variable to see the value options.

    set FPGA_FAMILY=xczu9eg
    
  5. Generate the bitstream

    generate_bitstream.bat
    

    This will generate a directory with the FPGA name and the TRD will be created in that directory.

Export Hardware (for SW development)

After the FPGA build is finished, an .xsa file has been automatically generated in the TRD directory. This file can be imported into Vitis to Create your own Vitis app for the board.