This design is targeted for xczu7ev board (part number: xczu7ev-fbvb900-2-i)

Zynq UltraScale+ Design Summary

Device	xczu7ev
SpeedGrade	-2
Part	xczu7ev-fbvb900-2-i
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	Quad SPI Flash	sclk_out	cmos	slow	disable	out	12
MIO 1	Quad SPI Flash	miso_mo1	schmitt	slow	pullup	inout	12
MIO 2	Quad SPI Flash	mo2	schmitt	slow	pullup	inout	12
MIO 3	Quad SPI Flash	mo3	schmitt	slow	pullup	inout	12
MIO 4	Quad SPI Flash	mosi_mi0	schmitt	slow	pullup	inout	12
MIO 5	Quad SPI Flash	n_ss_out	cmos	slow	disable	out	12
MIO 6	Feedback Clk	clk_for_lpbk	cmos	slow	disable	out	12
MIO 7	Quad SPI Flash	n_ss_out_upper	cmos	slow	disable	out	12
MIO 8	Quad SPI Flash	mo_upper[0]	schmitt	slow	pullup	inout	12
MIO 9	Quad SPI Flash	mo_upper[1]	schmitt	slow	pullup	inout	12
MIO 10	Quad SPI Flash	mo_upper[2]	schmitt	slow	pullup	inout	12
MIO 11	Quad SPI Flash	mo_upper[3]	schmitt	slow	pullup	inout	12
MIO 12	Quad SPI Flash	sclk_out_upper	cmos	slow	disable	out	12
MIO 13	SD 0	sdio0_data_out[0]	schmitt	slow	disable	inout	12
MIO 14	SD 0	sdio0_data_out[1]	schmitt	slow	disable	inout	12
MIO 15	SD 0	sdio0_data_out[2]	schmitt	slow	disable	inout	12
MIO 16	SD 0	sdio0_data_out[3]	schmitt	slow	disable	inout	12
MIO 17	SD 0	sdio0_data_out[4]	schmitt	slow	disable	inout	12
MIO 18	SD 0	sdio0_data_out[5]	schmitt	slow	disable	inout	12
MIO 19	SD 0	sdio0_data_out[6]	schmitt	slow	disable	inout	12
MIO 20	SD 0	sdio0_data_out[7]	schmitt	slow	disable	inout	12
MIO 21	SD 0	sdio0_cmd_out	schmitt	slow	disable	inout	12
MIO 22	SD 0	sdio0_clk_out	cmos	slow	disable	out	12
MIO 23	SD 0	sdio0_bus_pow	cmos	slow	pullup	out	12
MIO 24	UART 1	txd	cmos	slow	disable	out	12
MIO 25	UART 1	rxd	schmitt	fast	pullup	in	12
MIO 26	GPIO1 MIO	gpio1[26]	schmitt	slow	pullup	inout	12
MIO 27	VIDEO REF CLK	videorefclk	schmitt	fast	pullup	in	12
MIO 28	PSS ALT REF CLK	pssaltrefclk	schmitt	fast	pullup	in	12
MIO 29	GPIO1 MIO	gpio1[29]	schmitt	slow	pullup	inout	12
MIO 30	GPIO1 MIO	gpio1[30]	schmitt	slow	pullup	inout	12
MIO 31	GPIO1 MIO	gpio1[31]	schmitt	slow	pullup	inout	12
MIO 32	GPIO1 MIO	gpio1[32]	schmitt	slow	pullup	inout	12
MIO 33	GPIO1 MIO	gpio1[33]	schmitt	slow	pullup	inout	12
MIO 34	GPIO1 MIO	gpio1[34]	schmitt	slow	pullup	inout	12
MIO 35	GPIO1 MIO	gpio1[35]	schmitt	slow	pullup	inout	12
MIO 36	GPIO1 MIO	gpio1[36]	schmitt	slow	pullup	inout	12
MIO 37	GPIO1 MIO	gpio1[37]	schmitt	slow	pullup	inout	12
MIO 38	GPIO1 MIO	gpio1[38]	schmitt	slow	pullup	inout	12
MIO 39	GPIO1 MIO	gpio1[39]	schmitt	slow	pullup	inout	12
MIO 40	GPIO1 MIO	gpio1[40]	schmitt	slow	pullup	inout	12
MIO 41	GPIO1 MIO	gpio1[41]	schmitt	slow	pullup	inout	12
MIO 42	GPIO1 MIO	gpio1[42]	schmitt	slow	pullup	inout	12
MIO 43	GPIO1 MIO	gpio1[43]	schmitt	slow	pullup	inout	12
MIO 44	GPIO1 MIO	gpio1[44]	schmitt	slow	pullup	inout	12
MIO 45	GPIO1 MIO	gpio1[45]	schmitt	slow	pullup	inout	12
MIO 46	GPIO1 MIO	gpio1[46]	schmitt	slow	disable	inout	12
MIO 47	GPIO1 MIO	gpio1[47]	schmitt	slow	disable	inout	12
MIO 48	GPIO1 MIO	gpio1[48]	schmitt	slow	disable	inout	12
MIO 49	GPIO1 MIO	gpio1[49]	schmitt	slow	disable	inout	12
MIO 50	GPIO1 MIO	gpio1[50]	schmitt	slow	disable	inout	12
MIO 51	GPIO1 MIO	gpio1[51]	schmitt	slow	disable	inout	12
MIO 52	USB 0	ulpi_clk_in	schmitt	fast	pullup	in	12
MIO 53	USB 0	ulpi_dir	schmitt	fast	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	schmitt	slow	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	schmitt	fast	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	schmitt	slow	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	schmitt	slow	pullup	inout	12
MIO 58	USB 0	ulpi_stp	cmos	slow	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	schmitt	slow	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	schmitt	slow	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	schmitt	slow	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	schmitt	slow	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	schmitt	slow	pullup	inout	12
MIO 64	GPIO2 MIO	gpio2[64]	schmitt	slow	pullup	inout	12
MIO 65	USB0 Reset	reset	cmos	slow	pullup	out	12
MIO 66	GPIO2 MIO	gpio2[66]	schmitt	slow	pullup	inout	12
MIO 67	GPIO2 MIO	gpio2[67]	schmitt	slow	pullup	inout	12
MIO 68	PCIE	reset_n	cmos	slow	pullup	out	12
MIO 69	GPIO2 MIO	gpio2[69]	schmitt	slow	pullup	inout	12
MIO 70	GPIO2 MIO	gpio2[70]	schmitt	slow	pullup	inout	12
MIO 71	GPIO2 MIO	gpio2[71]	schmitt	slow	pullup	inout	12
MIO 72	GPIO2 MIO	gpio2[72]	schmitt	slow	pullup	inout	12
MIO 73	GPIO2 MIO	gpio2[73]	schmitt	slow	pullup	inout	12
MIO 74	I2C 0	scl_out	schmitt	slow	pullup	inout	12
MIO 75	I2C 0	sda_out	schmitt	slow	pullup	inout	12
MIO 76	GPIO2 MIO	gpio2[76]	schmitt	slow	pullup	inout	12
MIO 77	GPIO2 MIO	gpio2[77]	schmitt	slow	disable	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2666.640
DPLL	PSS_REF_CLK	2399.976
VPLL	PSS_REF_CLK	2999.970
RPLL	PSS_REF_CLK	2999.970
IOPLL	PSS_REF_CLK	2399.976

Peripheral	Requested Frequency (MHz)	Source	Actual Frequency (MHz)
USB0 freq (MHz)	250	RPLL	249.997498
QSPI freq (MHz)	300	IOPLL	299.997009
SDIO0 freq (MHz)	200	IOPLL	199.998001
SDIO1 freq (MHz)	200	IOPLL	199.998001
UART0 freq (MHz)	100	IOPLL	99.999001
UART1 freq (MHz)	100	IOPLL	99.999001
I2C0 freq (MHz)	100	IOPLL	99.999001
I2C1 freq (MHz)	100	IOPLL	99.999001
SPI0 freq (MHz)	200	IOPLL	199.998001
SPI1 freq (MHz)	200	IOPLL	199.998001
CAN0 freq (MHz)	100	IOPLL	99.999001
CAN1 freq (MHz)	100	IOPLL	99.999001
CPU_R5 freq (MHz)	500	RPLL	499.994995
IOU_SWITCH freq (MHz)	267	RPLL	249.997498
LPD_SWITCH freq (MHz)	500	RPLL	499.994995
LPD_LSBUS freq (MHz)	100	IOPLL	99.999001
TIMESTAMP freq (MHz)	100	IOPLL	99.999001
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	20	IOPLL	19.999800
PCAP freq (MHz)	200	IOPLL	199.998001
DBG_LPD freq (MHz)	250	RPLL	249.997498
ADMA freq (MHz)	533.4	RPLL	499.994995
PL0 freq (MHz)	100	IOPLL	99.999001
PL1 freq (MHz)	150	IOPLL	149.998505
PL2 freq (MHz)	200	IOPLL	199.998001
PL3 freq (MHz)	300	IOPLL	299.997009
AMS freq (MHz)	50	IOPLL	49.999500
ACPU freq (MHz)	1334	APLL	1333.320068
DBG FPD freq (MHz)	200	IOPLL	199.998001
PCIE freq (MHz)	250	RPLL	249.997498
DDR_CTRL freq MHz)	600.000	DPLL	599.994019
GPU freq (MHz)	600	DPLL	599.994019
GDMA freq (MHz)	667	DPLL	599.994019
DPDMA freq (MHz)	667	DPLL	599.994019
TOPSW_MAIN freq (MHz)	533.4	APLL	444.440033
TOPSW_LSBUS freq (MHz)	100	DPLL	99.999001
DBG TSTMP freq (MHz)	200	IOPLL	199.998001

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	1200	--
MEMORY TYPE	DDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	64 Bit	Data width of DDR interface, not including ECC data width
ECC	Enabled	Enables error correction code support
SPEED BIN	DDR4_2400T	Speed Bin
CL	17	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	16	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	17	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	17	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	46.16	Row cycle time (ns)
T RAS MIN	32	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	30.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	16 Bits	Width of individual DRAM components
DEVICE CAPACITY	8192 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	1	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	2	Number of bank address pins
ROW ADDR COUNT	16	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0xFFFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
PCIe	GT Lane0	Ref Clk0	100
USB0	GT Lane2	Ref Clk2	26