Dyplo stands for Dynamic Process Loader and is an operating system on FPGA fabric. Dyplo provides on demand reconfigurable function blocks on the FPGA, wrapped in a high-performance and effective Network-on-Chip. This allows you to reuse the same FPGA logic for multiple functions over time, resulting in a decrease of FPGA sizes and thus lower power consumption.
The functionalities of the function blocks can be programmed in C/C++ and compiled to FPGA code using a High-Level-Synthesis (HLS) tool. It is also possible to develop the functionality using VHDL or Verilog or to apply IP blocks from the Xilinx IP catalog. The logic interfaces are compliant to AXI4-Stream specifications. A typical software application will identify functionality that should run on an FPGA accelerator and wrap the software code with OpenCL type of commands. Then you can deploy the function on a partial in the FPGA, interconnect the data routes as file streams and execute the application. The behavior programming is similar to programming GPU based accelerator boards, but much faster.
Applications that benefit from Dyplo require FPGA type of algorithmic acceleration for achieving the software performance goals. Using Dyplo, you reduce the complexity of programming FPGA fabric to the level of programming GPU devices using OpenCL style of programming. If you would like to get to know and learn to work with Dyplo, you can follow a training program, given by our experienced TOPIC consultants. This gives you hands-on experience and an opportunity to profit from their modelling expertise for the most efficient coding style of C/C++ for using HLS.