Dyplo®, our Dynamic Process Loader, enables developers to connect to various processing units of choice while dynamically loading, distributing and controlling tasks. Dyplo® is a part of the Topic ecosystem of software solutions, System on Modules, carrier boards, development kits and IP blocks that are all compatible and combinable. Because you can move functionality across the platform when performance issues arise or are identified, Dyplo® enables you to postpone architectural choices to a later stage.

Next step in data and signal acceleration

Dyplo® paves the way for the next step in data and signal acceleration, simplifies development and enables out-of-the-box integration of CPU & FPGA. FPGA programming is also made software-friendly and with plug-in IP blocks, there is zero integration effort. Dyplo® reduces development time and with integration issues taken care of and a common language used across the whole CPU and FPGA platform, this new way of working will result in considerable savings.

Cases Dyplo®

  • BOM: proven 20% by tested use case.
    • In general significant BOM reduction due to re-use of FPGA fabric
    • Zynq® integration related cost savings
  • Development time: proven 30% by tested use case
    • Out-of-the box integration of CPU & FPGA
    • FPGA programming accessible for software developers
    • Shorter time to market
  • Power reduction by using FPGA technology
  • FPGA size reduction by re-using parts of your FPGA

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